The present invention relates generally to semiconductor device processing and, more particularly, to a structure and method for eliminating time dependent dielectric breakdown failure of low-k material.
In the fabrication of integrated circuit devices, it is often desirable to isolate individual components of the integrated circuits from one another with insulative materials. Such insulative materials may include, for example, silicon dioxide, silicon nitride and silicon carbide. While these materials may have acceptable insulating properties in many applications, they also have relatively high dielectric constants, which can lead to capacitive coupling between proximate conductive elements. This is particularly disadvantageous, given the ever-decreasing distances between conductive circuit elements, and the use of multi-layered structures. An unnecessary capacitive coupling between adjacent wires increases the RC time delay of a signal propagated therethrough, resulting in decreased device performance. Thus, for specific applications, insulating materials having relatively low dielectric constants (e.g., k less than 3) are desired. In very large scale integrated circuit (VLSI) technology, silicon dioxide (SiO2) has been traditionally used as an interlevel dielectric (ILD) material in conjunction with aluminum interconnect material. More recently, significant advancements have been made to enhance circuit performance by replacing the SiO2 with a xe2x80x9clow-kxe2x80x9d dielectric and by using copper (higher conductivity) interconnect.
Certain organic polymers are known in the semiconductor manufacturing industry for their low-k dielectric properties; these polymers are often used for intermetallic insulation in damascene structures. These polymers are generally classified as aromatic thermosets, polyarylene ethers and crosslinked polyphenylene polymers, including low-k organic and/or non-organic, porous or non-porous dielectric materials. The low-k dielectric is typically applied to semiconductor wafers by spin-on coating in a wafer track, similar to the process used in the application of photolithography resist. Alternatively, it may be deposited by a chemical vapor deposition (CVD) process.
However, the integration of an all low-k dielectric in semiconductor manufacturing has presented several challenges such as, for example, the effects of time dependent dielectric breakdown (TDDB). TDDB has been a substantial reliability concern in the formation of back end of line (BEOL) interconnect structures, when using a low-k dielectric in conjunction with copper metallization. However, the leakage current increases over time to a level sufficient to cause dielectric breakdown, and eventually circuit failure could occur over the lifetime of the device. This mode of failure is substantially absent in case of oxide dielectrics, but is predominant in copper interconnects formed within low-k dielectrics used as interlevel dielectric. Accordingly, it is desirable to be able to utilize a low-k dielectric material with a diffusive metallization material, while also preventing TDDB concerns.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by an interconnect structure for a device. A metallization line is formed within a low-k dielectric material, the metallization line being surrounded on bottom and side surfaces thereof by a liner material. An embedded dielectric cap is formed over a top surface of the metallization line, wherein the embedded dielectric cap has a sufficient thickness so as to separate a top surface of the liner material from a hardmask layer formed over the low-k dielectric material.
In another aspect, a back end of line (BEOL) interconnect structure for a semiconductor device includes a trench formed within a low-k dielectric material and a liner material formed within the trench. A metallization line formed within the trench, the metallization line being surrounded on bottom and side surfaces thereof by the liner material. An embedded dielectric cap is formed in the trench and over a top surface of the metallization line, wherein the embedded dielectric cap has a sufficient thickness so as to separate a top surface of the liner material from a hardmask layer formed over the low-k dielectric material.
In still another aspect, a method for forming an interconnect structure includes defining a trench within a low-k dielectric material and forming a liner material within the trench. A conductive metallization material is formed within the trench and over the liner, and a portion of the metallization material and the liner material is removed from the trench. An embedded dielectric cap is formed in the trench and over a top surface of the metallization material and the liner material, wherein the metallization material is surrounded on bottom and side surfaces thereof by the liner material, and surrounded on a top surface thereof by the embedded dielectric cap.